1. Field
The present technology relates to semiconductor packaging.
2. Description of Related Art
The strong growth in demand for portable consumer electronics is driving the need for high-capacity storage devices. Non-volatile semiconductor memory devices, such as flash memory storage cards, are becoming widely used to meet the ever-growing demands on digital information storage and exchange. Their portability, versatility and rugged design, along with their high reliability and large capacity, have made such memory devices ideal for use in a wide variety of electronic devices, including for example digital cameras, digital music players, video game consoles, PDAs and cellular telephones.
While a wide variety of packaging configurations are known, flash memory storage cards may in general be fabricated from so-called 3-D semiconductor devices. Such devices include for example a system-in-a-package (SiP) or a multichip module (MOM), where a plurality of die are mounted on a substrate in a stacked configuration. Edge views of conventional 3-D semiconductor packages 20 (without molding compound) are shown in prior art FIGS. 1 and 2. Typical packages include a plurality of semiconductor die 22 mounted to a substrate 26. In the examples shown, the die stack has four die, 22a, 22b, 22c and 22d. Further examples have more or less die in the stack. Although not shown in FIGS. 1 and 2, the semiconductor die 22 are formed with die bond pads on an upper surface of the die. Substrate 26 may be formed of an electrically insulating core sandwiched between upper and lower conductive layers. The upper and/or lower conductive layers may be etched to form conductance patterns including electrical leads and contact pads. Wire bonds 30 are thermosonically welded between the die bond pads of the semiconductor die 22 and the contact pads of the substrate 26 to electrically couple the semiconductor die to the substrate. The electrical leads on the substrate in turn provide an electrical path between the die and a host device. Once electrical connections between the die and substrate are made, the assembly is then typically encased in a molding compound to provide a protective package.
It is known to stack semiconductor die 22 on top of each other either with an offset configuration (prior art FIG. 1) or in an aligned configuration (prior art FIG. 2). In the offset configuration of FIG. 1, the die 22 are stacked with an offset so that the bond pads of the next lower die are left exposed and accessible to a wire bonding device. Such configurations are shown for example in U.S. Pat. No. 6,359,340 to Lin, et al., entitled, “Multichip Module Having a Stacked Chip Arrangement,” which patent is incorporated herein by reference in its entirety. An offset configuration provides an advantage of convenient access to the bond pads on each of the semiconductor die. However, the offset requires a greater footprint on the substrate, where space is at a premium.
In the aligned configuration of prior art FIG. 2, the semiconductor die 22 are stacked directly on top of each other, thereby taking up less footprint on the substrate as compared to an offset configuration. However, in an aligned configuration, space must be provided between adjacent semiconductor die for the bond wires 30. In addition to the height of the bond wires 30 themselves, additional space must be left above the bond wires, as contact of the bond wires 30 of one die with the next die above may result in an electrical short. As shown in FIG. 2, it is therefore known to provide dielectric spacer layers 34 to provide enough room for the bond wires 30 to be bonded between adjacent die 22. The requirement of the spacer layers adds height to the die stack and is a limiting factor in the number of die which may be included in the stack to still fit within the height of a standard memory card form factor.
While the wiring configuration shown in prior art FIGS. 1 and 2 may be possible for semiconductor with smaller numbers of die in the die stack, wiring of the die in die stacks of greater than four die becomes more problematic. In addition to vertical wire bonds, wire bonds may need to be made diagonally and/or additional substrate contact pads may be required. Prior art FIGS. 3 and 4 are top and side views of a typical NAND semiconductor package 20 (without molding compound) including eight die mounted to a substrate 26. FIG. 3 shows arbitrary x-y axes. Conventionally, the die 22 are stacked one atop another in an offset along the x-axis starting with die 0 and proceeding sequentially to die 7.
As noted, the substrate 26 includes contact pads, such as contact pads 38 shown in prior art FIG. 3. A die stack including a large number of die may need two sets of contact pads 38 to affect the input/output (I/O) to the die in the stack. In the example of FIGS. 3 and 4, the corresponding die bond pads 40 on respective die 0-3 are connected to each other, and to a first set of contact pads 38a on substrate 26 via a set of wire bonds 30a extending from bond pads 40 of die 0 to the contact pads 38a. As used herein, “corresponding” die bond pads on different die refer to die bond pads on different die that are aligned with each other along the y-axis. Thus, from the perspective of FIG. 3, the first (bottom-most) die pad on each die 0-3 correspond with each other and are wire bonded together, the second bottom-most die pad on each of die 0-3 correspond with each other and are wire bonded together, etc.
Similarly, corresponding die bond pads 40 on respective die 4-7 are connected to each other, and to a second set of contact pads 38b on substrate 26 via a set of wire bonds 30b extending from bond pads 40 of die 4 to the contact pads 38b. In the embodiment shown, the contact pads 38a may alternate with the contact pads 38b on the substrate. With such a wiring configuration, wire length for the wire bonds will be long, and wire-to-wire spacing between die in the stack may become smaller to the point where electrical shorting between wires occurs. This results in package failure and an adverse affect on assembly yield.
To minimize the above-described problems, die-stack rotation is employed as shown in the top and side views of prior art FIGS. 5 and 6. In the example of FIGS. 5 and 6, a first set of die 0-3 are offset stacked in a first direction, and connect to a set of contact pads 38a on a first side of the substrate 26 via wire bonds 30a. A second set of die 4-7 are offset stacked in a second direction opposite the first direction, and connect to a set of contact pads 38b on a second side of the substrate 26 opposite the first side via wire bonds 30b. 
One drawback with die-stack rotation is that the first set of die 0-3 are attached and wire bonded, and then the second set of die 4-7 are attached and wire bonded. The multiple die attach and wire bonding processes increase cycle time, and cause lower assembly yield due to more handling of the semiconductor packages during fabrication. There is a need for a die stack design allowing two sets of die to wire bond to two sets of contact pads on the substrate, while avoiding the above-described problems.
Another drawback to conventional stacked packages is exposure of bond wires outside of the final encapsulated package. This problem is specific to memory packages with irregular package outlines, such as microSD and MsMicro. Prior art FIGS. 7 through 9 show an example of a stacked die in a microSD memory package 20. FIGS. 7 and 9 further show a controller die 50 atop the die stack. The die stack may be assembled using die-stack rotation as described above and as shown in FIG. 9. In such embodiments, a substrate may have contact pads 38a along a first edge of the package which align with adjacent die bond pads of the first set of die as shown along edge 40 in FIG. 7. However, given the irregular shape of the package, for example along edge 42 of the package 20, some die bond pads are connected to contact pads 38b which are diagonally spaced away from their connected die bond pads. FIG. 8 shows an enlarged view of area 8-8 in FIG. 7. When the substrate is encapsulated and singulated in the final shape of the package, one or more wire bonds (such as wire bond 30a) along the irregular shaped edge 42 may reside outside of the encapsulation, or otherwise impermissibly close to the package edge. There is a need for a die stack design allowing efficient wire bonding along an irregular shaped edge of a package without exposing wires outside of the finished, encapsulated package.